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FabQED™ stakes indication

When an excursion starts, the clock is not only technical.

A wafer excursion is a deviation from the intended process window. See how delayed detection expands suspect WIP, inspection load, quarantine posture, and proof burden before the customer-safe response is ready.

Process-window deviationQuarantine and inspectionYield exposureCustomer-safe proof

Open stakes assessment Start exploring the platform

Excursion stakes clock

Adjust the scenario. See how operational pressure grows.

Public assumptions only. The point is not cost accounting; it is showing how fast exposure, customer obligations, and evidence burden converge.^1,2,3,8,9,10

Build the excursion scenario

Set the public assumptions and watch exposure update immediately.

What the clock represents

An excursion turns process deviation into quarantine, inspection, yield, and proof pressure.

Early detection limits the suspect population; delayed containment expands WIP exposure, inspection load, and the customer-safe evidence burden.

What an excursion is^7,10A process-window deviation that may affect one wafer, a subset of wafers, or a broader suspect population until scope is proven.

Containment load^8,11Suspect material moves into quarantine, focused inspection, rework, discard, or controlled release review.

Inspection pressure^3,4,11Higher-sensitivity detection can reduce escape risk while increasing inspection capacity and cycle-time pressure.

Yield and proof burden^6,7,18,19The team must bound affected wafers, quantify exposure, explain uncertainty, and support what is safe to tell the customer.

Processed wafer value^1,2$16,988 / wafer

Sampling / inspection posture^5,8,10,11Focused quarantine path

Impacted wafers⁵100Scrap / kill rate100 %Daily exposure before containment100 wafersDays until detection / containment^8,9,10,113 days

Direct wafer value at risk^1,2$1.7M100 wafers at 100% impact using 5nm public estimate.

Expected response windowResponse clock pressure^8,9,10,11Proof pressure building

300 additional wafers enter the exposure window before containment at this setting.

Inspection posture^5,8,10,11High-sensitivity inspection

Higher sensitivity pulls more suspect wafers into inspection, rework, or disposition review.

Added exposure if delayed^1,2$5.1M

Lots affected⁵4.0

Total wafers at risk400

Quarantine population^8,11400

Inspection load^3,4,11680

Rework / disposition pull^6,8,11400

Wafer-step equivalents^3,4100k

Response clock

The first proof obligations compress into hours and days.^8,9,10,11

0-24hAcknowledge and contain^8,9,11

Set the customer-safe posture, suspect scope, owner path, and first evidence asks.

5-15dRoot cause and corrective plan^8,9,10

Move from symptom control to supported cause, escape logic, and corrective-action plan.

20-45dImplement and prove closure^7,9,10

Show implemented controls, recurrence prevention, effectiveness proof, and signed closure.

Industry basis

Public supplier-quality expectations ground the response posture.

Industry-level execution problem

High-value WIP, rapid communication, and documented corrective action converge.^3,8,9,10,11

Public semiconductor and supplier-quality sources point to the same pattern: operational disruption can become customer-trust risk unless containment, evidence, corrective action, and communication move together.^{12,13,14,15,17,18,19}

Foundry disruption disclosures^12,13Public semiconductor disclosures show wafer scrap and production disruption can affect loss posture, recovery planning, and inspection controls.

Supplier quality communication^14,15,16Supplier-quality materials emphasize quality communications, long-term relationships, feedback, and corrective action plans.

QMS and corrective action^17,18Quality handbooks emphasize QMS discipline, supplier audits, containment, customer requirements, documentation, and timely correction.

Customer-specific requirements^19,20Supplier requirements extend customer-specific expectations through the supply chain and call for rapid notification of potential quality or supply-chain issues.

FabQED™ outcome path

Convert impact pressure into governed containment, evidence, ownership, and customer-safe proof.

Where FabQED™ changes the outcome

The response only matters when it becomes provable.

Containment boundary^8,11Separate suspect WIP, inventory, customer lots, and release posture.

Evidence plan^7,10Ask for the tests, inspections, genealogy, and records that prove the next claim.

Owner path^8,9Bind each move to a person, due posture, decision gate, and escalation condition.

Customer-safe proof^7,18,19Keep external communication inside approved facts and known uncertainty.

Without governed execution

Timeline reconstructed manually.
Evidence scattered across people and systems.
Ownership shifts during escalation.
Customer updates can outrun proof.
Closure is hard to replay later.

With FabQED

Signal-to-proof path is structured.
Claims are tied to evidence before advancement.
Next technical check is explicit and owned.
AI proposes; humans decide; evidence signs.
Closure becomes customer-safe and replayable.

Mitigation levers

Keep the response centered on exposure control, inspection capacity, and proof readiness.

Practical response moves

Containment quality is a timing, traceability, and capacity problem.

Strengthen early detection^3,4Use in-line metrology and defect inspection where a late miss can expand WIP exposure.

Improve traceability and quarantine^8,11Flag affected wafers and isolate suspect inventory, WIP, in-transit material, and downstream commitments.

Tune sampling posture^5,8,10Balance throughput against escape tolerance; higher-risk flows justify more aggressive sampling and inspection.

Scale inspection capacity^3,4,11When more wafers enter high-sensitivity review, the bottleneck shifts from detection to inspection throughput.

Assumptions and references

Keep the model public-safe, bounded, and auditable.

Citation stack

Directional public basis only; customer-specific economics, obligations, and contractual requirements govern actual use.

1
CSET / TechSpot5nm and 7nm wafer-value estimates: $16,988 and $9,346 per 300mm wafer.
2
Tom's Hardware / IBSReported estimates for ~$20,000 3nm wafers and ~$30,000 2nm wafers.
3
Semiconductor Industry AssociationUp to 1,400 wafer steps; 12-week average cycle time, 14-20 weeks for advanced processes, and up to 26 weeks finished-chip lead time.
4
SIA PFAS ConsortiumLeading devices can require more than 2,000 process steps, hundreds of production materials, and long manufacture/test windows.
5
Tu & Lu, Procedia EngineeringWafer-fab lot-size discussion referencing the 25-wafer lot convention and rising process-step complexity.
6
AnySiliconSimplified cost-per-good-die formula and yield-cost relationship.
7
ASQ8D problem-solving structure: containment, verified root cause, corrective action, validation, and prevention.
8
onsemi Supplier HandbookSupplier CAPA expectations, containment action within 24 hours, and detailed corrective action planning in 8D format.
9
MAHLE 8D Process1-5-20 supplier-feedback rule: 24-hour containment, 5-working-day root cause / corrective action, and 20-working-day implementation / prevention.
10
Oshkosh 8D Corrective ActionExample cadence for containment, root-cause identification, corrective action, validation, and closure.
11
Graco SCAR guidanceInventory, WIP, in-transit review, immediate actions, and containment plan expectations.
12
TSMC press release, Feb. 15, 2019Photoresist material incident, yield deviation, wafer scrap, Q1 impact, and strengthened inspection / incoming-material controls.
13
TSMC press release, Feb. 10, 2025Earthquake and aftershocks impacted wafers in process, caused scrap, and led to an estimated related loss net of insurance claim.
14
Intel Supplier Quality PortalQuality applications and related information intended to improve quality-related communications with suppliers.
15
Intel Information for Potential SuppliersLong-term supplier relationships, quality and productivity expectations, measures of success, feedback, and corrective action plans.
16
Intel 2025 Form 10-KFoundry trust depends on high-quality, reliable, high-yield manufacturing services and rigorous quality systems.
17
Samsung Semiconductor Quality HandbookQMS discipline, supplier audits, investigation, corrective action, preventive measures, and timely containment.
18
Samsung Supplier Code of ConductCustomer requirements, risk management, communication, timely correction, documentation, and records.
19
Micron Supplier Requirements StandardMinimum quality, business-process, manufacturing, compliance, documentation, and customer-specific supply-chain requirements.
20
Micron press release, July 11, 2022Hiroshima power disruption, shutdown protocols, WIP assessment, expected production-output loss, cost impact, and wafer scrap.